A precharge mechanism is commonly used in typical static memory architectures. For instance, in most high-speed Static Read Access Memory (SRAM) architecture, both the bitlines of the memory are initially precharged to the high voltage level. While reading a location in the memory, one of the wordlines corresponding to the location is selected enabling the access transistor and connecting the bitline to a memory cell. The memory cell storing a low voltage discharges the bitline producing current on the bitline in the process. Based on the current or voltage output of the memory cell, it is sensed by the sense amplifier as a low value stored in the memory.
FIG. 1 shows circuitry for a bit in a conventional memory structure. The circuitry comprises bitlines BIT and BITBAR, memory cells with access transistors and wordlines associated with each memory cell. The two access transistors are coupled to each memory cell on one end and to the common bitlines BIT and BITBAR respectively on the other end. The gate node of access transistor is coupled to the associated wordline. While reading, one wordline is selected and other wordlines are connected to ground through the wordline drivers. The bitline connected to low node discharges through the pull down of selected memory cell while bitline bar is held high. A problem with such setup may arise when memory cells other than the one selected in the column have opposite data values written in them. In this situation, bitline bar discharges through the leakage in the access transistors of these cells, and the worst case is when all other cell of column have opposite data. This may result in erroneous detection of the stored data by the sense amplifier.
As the technology is resulting in smaller semiconductor devices, the leakage current in the access transistors has become a prime concern. The leakage current has become of same order as the current of the devices. The increased leakage current can be attributed to increase in the subthreshold current as technology has moved to deep-sub micron regime. At high temperature, the problem is even more severe and has become a bottleneck for fast and reliable operation of data sensing. The worst case is when one cell is read and the opposite of this cell data is stored in all other cells in the column.
There are some approaches for reducing leakage current such as use of a high threshold transistor, stack access for memory cells, but all these either need modified process or reduce speed due to two access in series. These techniques also result in bigger chip area. Hence there is need for memory with reduced bitline leakage current. At the same time, there is also need for memories that provide reduced complexity and silicon area. There is also need for a memory architecture that does not result in reduced memory speed as a result of leakage current reduction.